CSC 173 Tues. Dec 3, 2002 ======================================= TAs for 170 and 172 next semester need A- or better in 172 see Marty Project 5 out, due on Monday Project 6 out this afternoon due next Friday written assignment, hand in either in my office or to Marty ======================================= Resolution The idea of resolution is simple: if we know p OR q and p -> r then we can deduce q OR r Put another way: (p OR q) AND (NOT p OR r) -> q OR r This is the *Resolution Tautology*. In order to apply resolution in a proof: 1. we express our hypotheses and conclusion as a product of sums (conjunctive normal form), such as those that appear in the Resolution Tautology. 2. each maxterm in the CNF of the hypothesis becomes a clause in the proof. 3. we apply the resolution tautology to pairs of clauses, producing new clauses. 4. if we produce all the clauses of the conclusion, we have proven it. ------------------------------------------------------------------------ Creating CNF 1) get rid of all operators except AND and OR 2) use DeMorgan's laws to push NOTs inward 3) distribute to push ORs inside ANDs ------------------------------------------------------------------------ Proofs by Contradiction using Resolution We can combine resolution with proof by contradiction (where we assert the negation of what we wish to prove, and from that premise derive FALSE) to direct our search towards smaller and smaller clauses, with the goal of producing FALSE. This approach (working toward smaller clauses) constitutes a heuristic that helps guide us toward an efficient proof. Proof by contradiction: (NOT p -> 0) == p We use proof by contradiction to drive our search for a proof; we are looking for the smallest possible goal clause (false), so any use of equivalences or resolution that brings us to simpler expressions is working towards that goal. We can redo the previous proof (about Joe and his umbrella) using proof by contradiction with resolution: 1. NOT r OR u Premise 2. NOT u OR NOT w Premise 3. r OR NOT w Premise 4. w Negation of conclusion 5. r 3, 4 resolution 6. u 1, 5 resolution 7. NOT w 2, 6 resolution 8. FALSE 4, 7 resolution ------------------------------------------------------------------------ Proof by Resolution: Example 2 If either C173 or C108 is required, then all students will take computer science. C173 and C252 are required. Prove that all students will take computer science. We formalize the proof as follows: P1. (C173 OR C108) -> ACS P2. C173 P3. C252 Prove: ACS We then rewrite our hypotheses in conjunctive normal form: P1: (NOT C173 OR ACS) (NOT C108 OR ACS) P2: C173 P3: C252 Then we use proof by contradiction, by asserting the clauses of the premises and the negation of the conclusion, and deriving false. 1. NOT C173 OR ACS Premise 2. NOT C108 OR ACS Premise 3. C173 Premise 4. C252 Premise 5. NOT ACS Negation of conclusion 6. NOT C173 1, 5 resolution 7. FALSE 3, 6 resolution ------------------------------------------------------------------------ Proof by Resolution: Example 3 Either Heather attended the meeting or Heather was not invited. If the boss wanted Heather at the meeting, then she was invited. Heather did not attend the meeting. If the boss did not want Heather there, and the boss did not invite her there, then she is going to be fired. Prove Heather is going to be fired. 1. A OR NOT I Premise 2. NOT W OR I Premise 3. NOT A Premise 4. W OR I OR F Premise 5. NOT F Negation of conclusion 6. W OR I 4, 5 resolution 7. I 2, 6 resolution, idempotence 8. A 1, 7 resolution 9. FALSE 3, 8 resolution ------------------------------------------------------------------------ Proof by Resolution: Example 4 Either taxes are increased or if expenditures rise then the debt ceiling is raised. If taxes are increased, then the cost of collecting taxes rises. If a rise in expenditures implies that the government borrows more money, then if the debt ceiling is raised, then interest rates increase. If taxes are not increased and the cost of collecting taxes does not increase then if the debt ceiling is raised, then the government borrows more money. The cost of collecting taxes does not increase. Either interest rates do not increase or the government does not borrow more money. Prove either the debt ceiling isn't raised or expenditures don't rise. 1. T OR NOT E OR D Premise 2. NOT T OR C Premise 3. (E AND NOT G) OR NOT D OR I Premise 4. T OR C OR NOT D OR G Premise 5. NOT C Premise 6. NOT I OR NOT G Premise 7. D AND E Negation of conclusion 8. (E AND NOT G) OR I L3, L7, resolution 9. C OR NOT D OR G L2, L4, resolution 10. C OR G L7, L9, resolution 11. G L5, L10, resolution 12. NOT I L6, L11, resolution 13. E AND NOT G L8, L12, resolution 14. NOT G L13, tautology 15. FALSE L11, L14, contradiction ------------------------------------------------------------------------ Proof by Resolution: Example 5 Reprise: If the weather is warm and the sky is clear, then either we go swimming or we go boating. It is not the case that if the sky is clear then we go swimming. Prove: if we do not go boating, then the weather is not warm. w = weather is warm c = sky is clear s = we go swimming b = we go boating premise 1: (w AND c) -> (s OR b) NOT (w AND c) OR (s OR b) (NOT w OR NOT c) OR (s OR b) (NOT w OR NOT c OR s OR b) premise 2: NOT (c -> s) NOT (NOT c OR s) c AND NOT s negated conclusion: NOT (NOT b -> NOT w) NOT (b OR NOT w) NOT b AND w 1. NOT w OR NOT c OR s OR b premise 1 2. c premise 2a 3. NOT s premise 2b 4. NOT b negated conclusion 1 5. w negated conclusion 2 6. NOT w OR s OR b 1 & 2 7. NOT w OR b 6 & 3 8. NOT w 7 & 4 9. FALSE 8 & 5 ------------------------------------------------------------------------ Prolog is a programming language based on the resolution principle. It isn't a pure realization of resolution -- there is no way to express negative terms as facts (only as possibilities), and (conversely) there are ways to express things beyond even first-order predicate calculus -- but basically it works by resolution. ======================================================================== Circuit Design A gate is a basic (indivisible) electronic device that computes a Boolean function. * A gate has one or more inputs (which are simply voltage levels) and produces an output (voltage level). * AND, OR, NOT, NAND, and NOR gates are particularly easy to implement electronically (with any number of inputs), and therefore are the gates used in practice. A circuit is a combination of gates, where the outputs of some gates are the inputs of others. * Each circuit may have one or more inputs, which are actually inputs to the gates in the circuit. * A circuit may have one or more outputs. ------------------------------------------------------------------------ Combinational vs Sequential Circuits Combinational circuits: * produce an output that is a boolean function (combination) of the input values. * are acyclic in that there are no cycles between the inputs of a gate and its outputs. * have no memory; there is no way to remember previous inputs or outputs. * are used to decode instructions and perform arithmetic. Sequential circuits: * produce an output that depends not only on the current input values, but also on the previous sequence of input values. * are cyclic; the output of a gate at some moment in time eventually feeds into the input of that gate at some future time. * can remember results of previous operations, and use those results as input. * are used to build registers and memory units. ------------------------------------------------------------------------ Combinational Circuit for an Encoder for a 7 Segment Display Consider a 7-segment display such as those used in most calculators: A ------- | | F | | B | G | ------- | | E | | C | | ------- D We would like to design a combinational circuit that takes 10 different inputs (corresponding to the decimal digits 0-9) labeled i0..i9 and lights up the display segments A-G as needed to display the decimal digit specified in the input. In particular, if input i0 is 1, then outputs A, B, C, D, E, and F should be 1 (producing a 0 on the display). The boolean expressions describing each of the outputs are: A = i0 + i2 + i3 + i5 + i7 + i8 + i9 B = i0 + i1 + i2 + i3 + i4 + i7 + i8 + i9 C = i0 + i1 + i3 + i4 + i5 + i6 + i7 + i8 + i9 D = i0 + i2 + i3 + i5 + i6 + i8 E = i0 + i2 + i6 + i8 F = i0 + i4 + i5 + i6 + i8 + i9 G = i2 + i3 + i4 + i5 + i6 + i8 + i9 We can build this circuit with 7 OR gates (one for each segment in the display) some of which take up to 9 inputs. ------------------------------------------------------------------------ A Sequential Circuit The following is a sequential circuit, because the output of the AND gate is an input to the OR gate and vice versa. x------------->| |AND)---*---> z *-->| | | | *--|-----------* | | | *-----------* | | *----->) | )OR>----* y ------------>) What does this circuit do? * If x = y = 1, then z=1. * If x=0, then z=0. * If x=1, and y=0, then the circuit depends on the previous value of z. The output of the circuit (z) is 1 if at some point in the past x and y were 1, and x has remained 1 ever since. ------------------------------------------------------------------------ Constraints on Circuit Design In designing efficient digital circuits there are numerous constraints to be considered, all of which impact the cost or speed of the resulting circuit. * Circuit speed: every gate in the circuit introduces a delay (which may be as small as 10^-10 seconds), so the number of gates on the path between the input and output determines how quickly the output will be computed. * Size limitations: the more gates we use in a circuit, the larger it will be. Large circuits are more expensive (in part because they have a higher failure rate) and slower, since signals must propagate from one end of the circuit to another, and the propagation speed is limited by the speed of light. * Fan-in and Fan-out: The fan-in and fan-out of a gate is the number of inputs and outputs, respectively. Large fan-in or fan-out makes for slower gates. ------------------------------------------------------------------------ A Ripple-Carry Adder We have already seen how to construct a one-bit adder, which takes two input operands (x and y) and a carry-in bit (ci), and produces the sum (z) and a carry-out bit (co). x y ci z co --------------------- 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 The logical expression for z is: (~x ~y ci) + (~x y ~ci) + (x ~y ~ci) + (x y ci) The logical expression for co is: (~x y ci) + (x ~y ci) + (x y ~ci) + (x y ci) A 32-bit ripple-carry adder is simply a sequence of 32 one-bit adders, where the carry-out bit from adder[i] provides the carry-in bit for adder[i+1]. The carry-in[0] is 0, and the sum is carry-out[31], z[31], z[30],..., z[0]. In a ripple-carry adder, the carry bits ripple through the circuit from adder[0] up to adder[31]. Thus, the delay of a ripple-carry adder of N bits is proportional to N. We would like to design an adder with a smaller delay, especially for larger word sizes (64 bits or more). ------------------------------------------------------------------------ Design of a Divide-and-Conquer Adder To add two N-bit numbers, we can use a divide-and-conquer approach in which we build a circuit that adds two N/2-bit numbers, and then use two such circuits and combine their results. To build a 32-bit adder, we would use two 16-bit adders to add the left and right halves of the operands in parallel, and then we would combine the results. * Each 16-bit adder would be composed of two 8-bit adders. * Each 8-bit adder would be composed of two 4-bit adders. * Each 4-bit adder would be composed of two 2-bit adders. * Each 2-bit adder would be composed of two 1-bit adders. Since we cannot know whether the lower half of the operands will result in a "carry" into the upper half, how can the two adders function in parallel? * we compute two sums for the upper half of the operands; one assuming there is a carry, and the other assuming there is no carry. * we use additional circuitry to select which of the two sums to use in the result. ------------------------------------------------------------------------ Design of an N-Adder Suppose we have two N-bit operands, expressed in binary form as x1..xN and y1..yN. We will design an N-adder that computes: * the sum without carry, s1..sN, the N-bit sum of x1..xN and y1..yN assuming no carry into the sum of xN and yN. * the sum with carry, t1..tN, the N-bit sum of x1..xN and y1..yN assuming there is a carry into the sum of xN and yN. * the carry-propagate bit, p, which is 1 if there is a carry out of the leftmost place (x1 and y1), on the assumption there is a carry into the rightmost place. * the carry-generate bit, g, which is 1 if there is a carry out of the leftmost place (x1 and y1) even if there is no carry into the rightmost place. We will first show how to build a 1-bit adder component, and then show how to build an N-adder out of 1-bit adders. ------------------------------------------------------------------------ A 1-bit Adder A 1-adder computes the following Boolean functions: x y s t p g -------------------------- 0 0 0 1 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 0 1 1 1 The corresponding logical expressions are: s = (~x y) + (x ~y) t = (~x ~y) + (xy) p = x + y g = xy ------------------------------------------------------------------------ A 2-bit Adder from 1-bit Adders We can build a 2-bit adder using two 1-bit adders. -------- x1 ------>| Low | -----> sL --------------------> s1 | Order| -----> tL --------------------> t1 y1 ------>| 1-bit| -----> gL -------* | Adder| -----> pL ----* | -------- | | | | | | | *--->|F|-----> g -------- *------>|I|-----> p x2 ------>| High | -----> sH ----------->|X|-----> s2 | Order| -----> tH ----------->|I|-----> t2 y2 ------>| 1-bit| -----> gH ----------->|T| | Adder| -----> pH ----------->| | -------- The sum of the low-order bits (s1 or t1) doesn't depend on whether there is a carry from the low-order bits to the high-order bits, so we compute the sum of x1 and y1 into sL and tL, and produce those values as the resulting sum of the low-order bits (with different assumptions about carry-in bits). The sum of the high-order bits (s2 and t2) does depend on whether there is a carry (gL and pL), so we take the carry bits from the first adder, and the summation results from the second adder, and combine them together in the circuit labeled FIXIT to get the final result. ------------------------------------------------------------------------ Combining the Results of 1-bit Adders FIXIT computes its outputs using the following expressions: * p = gH + pH pL: that is, if there is a carry into the low-order part of the circuit, there is a propagation carry out of the high-order part of the circuit if both the lower-order and high-order bits propagate a carry (pH pL) or if there is a carry out of the high-order bits (gH). * g = gH + pH gL: that is, if there is no carry into the low-order part of the circuit, there is a carry out of the high-order part if there is a carry out of the high-order bits anyway (gH) or if there is a carry from the low-order bits (gL), and the high-order bits propagate that carry (pH). * s2 = (sH ~gL) + (tH gL): that is, the sum of the high order bits (under the assumption of no carry in from the right end of the circuit) is sH if there is no carry generated from the low-order bits, and tH otherwise. * t2 = (sH ~pL) + (tH pL): that is, the sum of the high order bits (under the assumption of a carry in from the right end of the circuit) is tH if there is a carry propagated through the low-order bits, and sH otherwise. We can generalize this construction to N bits, and create an N-adder where the circuit delay is 3(log N + 1), rather than the O(N) delay in the ripple-carry adder.