HASDEL Process

The Figure 1 summarizes the HASDEL approach. The engineering teams capture the system architecture thanks to SLIM, a language very close from AADL. SLIM allows modelling the processors, the communication network, the devices (sensors and actuators), the software, etc... When needed, the electrical modes of the equipment (powered, not powered, booting...) and their functional modes are captured by timed finite state machines. The RAMS engineers complete thus this engineering model with specific timed error models and fault injections. This model can then be used to perform RAMS analysis (thanks to model checking, formal proof, generation of timed failure propagation graphs, FTA, FMEA...). HASDEL Process

Main Features

The HASDEL modelling is based on an extension of the AADL (“Architecture Analysis Design Language”) language. Once the nominal and error models have been modelled, the System/RAMS Engineer can interact with the following use-cases and activities:

HASDEL Environment

The following figure shows the general workflow in the HASDEL Environment. HASDEL Environment Workflow The main activities and the control flow are as follows: